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8/23/04 notes through are on page 7 description this digital audio hexfet ? is specifically designed for class-d audio amplifier applications. this mosfet utilizes the latest processing techniques to achieve low on-resistance per silicon area. furthermore, gate charge, body-diode reverse recovery and internal gate resistance are optimized to improve key class-d audio amplifier performance factors such as efficiency, thd and emi. additional features of this mosfet are 175c operating junction temperature and repetitive avalanche capability. these features combine to make this mosfet a highly efficient, robust and reliable device for class-d audio amplifier applications. features advanced process technology key parameters optimized for class-d audio amplifier applications low r dson for improved efficiency low q g and q sw for better thd and improved efficiency low q rr for better thd and lower emi 175c operating junction temperature for ruggedness repetitive avalanche capability for robustness and reliability lead-free s d g
v ds -55 v r ds(on) typ. @ v gs = -10v 93 m r ds(on) typ. @ v gs = -4.5v 150 m q g typ. 31 nc t j max 175 c key parameters IRLIB9343PBF to-220 full-pak absolute maximum ratings parameter units v ds drain-to-source voltage v v gs gate-to-source voltage i d @ t c = 25c continuous drain current, v gs @ -10v a i d @ t c = 100c continuous drain current, v gs @ -10v i dm pulsed drain current p d @t c = 25c power dissipation w p d @t c = 100c power dissipation linear derating factor w/c t j operating junction and c t stg storage temperature range mounting torque, 6-32 or m3 screw lbf in (n m ) thermal resistance parameter typ. max. units r jc junction-to-case ??? 3.84 c/w r ja junction-to-ambient ??? 65 max. -10 -60 20 -55 -14 -40 to + 175 10 (1.1) 33 20 0.26 www.vishay.com 1 document number: 91339

s d g electrical characteristics @ t j = 25c (unless otherwise specified) parameter min. typ. max. units bv dss drain-to-source breakdown voltage -55 ??? ??? v ? v dss / ? t j breakdown voltage temp. coefficient ??? -52 ??? mv/c r ds(on) static drain-to-source on-resistance ??? 93 105 m ? ??? 150 170 v gs(th) gate threshold voltage -1.0 ??? ??? v ? v gs(th) / ? t j gate threshold voltage coefficient ??? -3.7 ??? mv/c i dss drain-to-source leakage current ??? ??? -2.0 a ??? ??? -25 i gss gate-to-source forward leakage ??? ??? -100 na gate-to-source reverse leakage ??? ??? 100 g fs forward transconductance 5.3 ??? ??? s q g total gate charge ??? 31 47 q gs pre-vth gate-to-source charge ??? 7.1 ??? v gs = -10v q gd gate-to-drain charge ??? 8.5 ??? i d = -14a q godr gate charge overdrive ??? 15 ??? see fig. 6 and 19 t d(on) turn-on delay time ??? 9.5 ??? t r rise time ??? 24 ??? t d(off) turn-off delay time ??? 21 ??? ns t f fall time ??? 9.5 ??? c iss input capacitance ??? 660 ??? c oss output capacitance ??? 160 ??? pf c rss reverse transfer capacitance ??? 72 ??? c oss effective output capacitance ??? 280 ??? l d internal drain inductance ??? 4.5 ??? between lead, nh 6mm (0.25in.) l s internal source inductance ??? 7.5 ??? from package avalanche characteristics parameter units e as single pulse avalanche energy mj i ar avalanche current a e ar repetitive avalanche energy mj diode characteristics parameter min. typ. max. units i s @ t c = 25c continuous source current ??? ??? -14 (body diode) a i sm pulsed source current ??? ??? -60 (body diode) v sd diode forward voltage ??? ??? -1.2 v t rr reverse recovery time ??? 57 86 ns q rr reverse recovery charge ??? 120 180 nc v gs = -4.5v, i d = -2.7a ??? 190 see fig. 14, 15, 17a, 17b v ds = v gs , i d = -250a v ds = -55v, v gs = 0v v ds = -55v, v gs = 0v, t j = 125c v gs = -20v v gs = 20v i d = -14a typ. max. ? = 1.0mhz, see fig.5 v gs = 0v, v ds = 0v to -44v v gs = 0v t j = 25c, i f = -14a di/dt = 100a/s t j = 25c, i s = -14a, v gs = 0v showing the integral reverse p-n junction diode. conditions v gs = 0v, i d = -250a reference to 25c, i d = -1ma v gs = -10v, i d = -3.4a mosfet symbol r g = 2.5 ? v ds = -25v, i d = -14a v ds = -44v conditions and center of die contact v dd = -28v, v gs = -10v v ds = -50v www.vishay.com 2 document number: 91339

fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics fig 4. normalized on-resistance vs. temperature fig 6. typical gate charge vs.gate-to-source voltage fig 5. typical capacitance vs.drain-to-source voltage 0.1 1 10 100 -v ds , drain-to-source voltage (v) 0.1 1 10 100 - i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 60s pulse width tj = 25c -2.5v vgs top -15v -12v -10v -8.0v -5.5v -4.5v -3.0v bottom -2.5v 0.1 1 10 100 -v ds , drain-to-source voltage (v) 0.1 1 10 100 - i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 60s pulse width tj = 175c -2.5v vgs top -15v -12v -10v -8.0v -5.5v -4.5v -3.0v bottom -2.5v 0.0 5.0 10.0 15.0 -v gs , gate-to-source voltage (v) 0.1 1.0 10.0 100.0 - i d , d r a i n - t o - s o u r c e c u r r e n t ( ) v ds = -25v 60s pulse width t j = 25c t j = 175c -60 -40 -20 0 20 40 60 80 100 120 140 160 180 t j , junction temperature (c) 0.5 1.0 1.5 2.0 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( n o r m a l i z e d ) i d = -14a v gs = -10v 1 10 100 -v ds , drain-to-source voltage (v) 10 100 1000 10000 c , c a p a c i t a n c e ( p f ) coss crss ciss v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd 0 1020304050 q g total gate charge (nc) 0 4 8 12 16 20 - v g s , g a t e - t o - s o u r c e v o l t a g e ( v ) v ds = -44v vds= -28v vds= -11v i d = -14a for test circuit see figure 19 www.vishay.com 3 document number: 91339

fig 11. maximum effective transient thermal impedance, junction-to-case fig 10. threshold voltage vs. temperature fig 9. maximum drain current vs. case temperature fig 7. typical source-drain diode forward voltage fig 8. maximum safe operating area 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -v sd , source-to-drain voltage (v) 0.1 1.0 10.0 100.0 - i s d , r e v e r s e d r a i n c u r r e n t ( a ) t j = 25c t j = 175c v gs = 0v -75 -50 -25 0 25 50 75 100 125 150 175 t j , temperature ( c ) 1.0 1.5 2.0 2.5 - v g s ( t h ) g a t e t h r e s h o l d v o l t a g e ( v ) i d = -250a 25 50 75 100 125 150 175 t j , junction temperature (c) 0 4 8 12 16 - i d , d r a i n c u r r e n t ( a ) 1e-006 1e-005 0.0001 0.001 0.01 0.1 1 10 t 1 , rectangular pulse duration (sec) 0.001 0.01 0.1 1 10 t h e r m a l r e s p o n s e ( z t h j c ) 0.20 0.10 d = 0.50 0.02 0.01 0.05 single pulse ( thermal response ) notes: 1. duty factor d = t1/t2 2. peak tj = p dm x zthjc + tc ri (c/w) i (sec) 0.8737 0.000799 0.877 0.068578 2.089 2.593 j j 1 1 2 2 3 3 r 1 r 1 r 2 r 2 r 3 r 3 c ci= i / ri ci= i / ri 1 10 100 1000 -v ds , drain-tosource voltage (v) 1 10 100 1000 - i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) tc = 25c tj = 175c single pulse 1msec 10msec operation in this area limited by r ds (on) 100sec www.vishay.com 4 document number: 91339

fig 13. maximum avalanche energy vs. drain current fig 12. on-resistance vs. gate voltage fig 14. typical avalanche current vs.pulsewidth fig 15. maximum avalanche energy vs. temperature notes on repetitive avalanche curves , figures 14, 15: (for further info, see an-1005 at www.irf.com) 1. avalanche failures assumption: purely a thermal phenomenon and failure occurs at a temperature far in excess of t jmax . this is validated for every part type. 2. safe operation in avalanche is allowed as long ast jmax is not exceeded. 3. equation below based on circuit and waveforms shown in figures 17a, 17b. 4. p d (ave) = average power dissipation per single avalanche pulse. 5. bv = rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. i av = allowable avalanche current. 7. ? t = allowable rise in junction temperature, not to exceed t jmax (assumed as 25c in figure 14, 15). t av = average time in avalanche. d = duty cycle in avalanche = t av f z thjc (d, t av ) = transient thermal resistance, see figure 11) p d (ave) = 1/2 ( 1.3bvi av ) = t/ z thjc i av = 2 t/ [1.3bvz th ] e as (ar) = p d (ave) t av 4.0 6.0 8.0 10.0 -v gs , gate-to-source voltage (v) 0 100 200 300 400 500 600 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( m ? ) t j = 25c t j = 125c i d = -14a 1.0e-06 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 tav (sec) 0.1 1 10 100 1000 - a v a l a n c h e c u r r e n t ( a ) 0.05 duty cycle = single pulse 0.10 allowed avalanche current vs avalanche pulsewidth, tav assuming ? tj = 25c due to avalanche losses. note: in no case should tj be allowed to exceed tjmax 0.01 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 200 400 600 800 1000 e a s , s i n g l e p u l s e a v a l a n c h e e n e r g y ( m j ) i d top -5.0a -5.6a bottom -10a 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 40 80 120 160 200 e a r , a v a l a n c h e e n e r g y ( m j ) top single pulse bottom 1% duty cycle i d = -10a www.vishay.com 5 document number: 91339

fig 19a. gate charge test circuit fig 19b gate charge waveform vds vgs id vgs(th) qgs1 qgs2 qgd qgodr fig 16.
for p-channel hexfet power mosfets
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data and specifications subject to change without notice. this product has been designed for the industrial market. qualification standards can be found on ir?s web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 08/04 repetitive rating; pulse width limited by max. junction temperature. starting t j = 25c, l = 3.89mh, r g = 25 ? , i as = -10a. pulse width 400s; duty cycle 2%. r is measured at t j of approximately 90c. limited by tjmax. see figs. 14, 15, 17a, 17b for repetitive avalanche information
to-220 fullpak packages are not recommended for surface mount application. to-220 full-pak part marking information with assembly example: this is an irfi840g lot code 3432 assembled on ww 24 1999 in the assembly line "k" part number lot code assembly int e r nat ional r e ct if ie r logo 34 32 924k irf i840g dat e code year 9 = 1999 week 24 line k note: "p" in assembly line position indicates "lead-free" to-220 full-pak package outline dimensions are shown in millimeters (inches) www.vishay.com 7 document number: 91339
legal disclaimer notice vishay document number: 99901 www.vishay.com revision: 12-mar-07 1 notice the products described herein were acquired by vishay intertechnology, inc., as part of its acquisition of international rectifier?s power control systems (pcs) business, which closed in april 2007. specifications of the products displayed herein are pending review by vishay and are subject to the terms and conditions shown below. specifications of the products displayed herein are subject to change without notice. vishay intertechnology, inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. information contained herein is intended to provide a product description only. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in vishay's terms and conditions of sale for such products, vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and /or use of vishay products including liab ility or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyrigh t, or other intellectual property right. the products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify vishay for any damages resulting from such improper use or sale. international rectifier ? , ir ? , the ir logo, hexfet ? , hexsense ? , hexdip ? , dol ? , intero ? , and powirtrain ? are registered trademarks of international rectifier corporation in the u.s. and other countries. all other product names noted herein may be trademarks of their respective owners.

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